Certuspro NX revolutionizes general purpose FPGA again

Lattice semiconductor's fourth nexus platform based product, certuspro NX, has brought significant innovation to the existing FPGA market. This series of FPGA is manufactured by 28 nm fd-soi process, which has the advantages of low power consumption and small size. It is mainly aimed at the low-density device market. Compared with the previously released certus NX, the logical unit of the new product has been increased from 17 K to 96 K. In 2020, the general FPGA market will be more diversified, and the market scale will increase by about 10%; Certuspro NX can be used to realize various functions, including 5g cellular network, artificial intelligence and Internet of things. These markets are constantly changing, and FPGA can provide powerful flexibility that ASIC does not have.
The new product series has two models, cpnx-50k has 52K logic unit; Cpnx-100k has 96k logic units and is also the first engineering sample. As shown in Figure 1, the latter model has a programmable I / O supporting lpddr4 DRAM (the first of its kind). Lattice also tripled the internal memory capacity, allowing certuspro NX to reduce power consumption when performing storage intensive operations.

Figure 1: certuspro NX block diagram. The new FPGA includes 7.3 MB on-chip memory, 156 18x18 multiplier DSP modules, programmable logic and 8 flexible 10Gbps SerDes channels (configurable connection to DisplayPort or coaxpress).
When designing certuspro NX series products, lattice adopted 28 nmfd SOI process. Although people have questioned this choice before, lattice has perfectly reached the standards of power consumption and soft error rate, which is very important for the company to win customers' multiple application designs. In addition to programmable logic, certuspro NX also has hard core modules, which can also reduce power consumption. It also includes a 10G Ethernet port and a four channel PCIe gen3 controller. Lattice also pays special attention to the bit stream configuration module, so its device startup speed is very fast, and the configuration can be completed in less than 30 milliseconds.
Compared with previous products, certuspro NX has greatly improved, enabling customers to realize advanced functions in their FPGA based design. Lattice doubled the number of logical units of the new product, expanded the capacity of on-chip memory, and upgraded PCIe controller and programmable I / O interface. Compared with Intel's cyclone V GT series and Xilinx's artix-7 series, the performance of the new products has reached the best in the industry.
Machine vision and network edge AI

In addition to expanding the programmable logic architecture of certuspro NX, lattice also strengthened the AI function of the platform. The new device uses 7.3 MB of internal memory. Customers can load lightweight neural networks to identify objects, monitor keywords or detect abnormal behavior. However, hardware is only one aspect of design. Lattice's sensai software collection can be used with Caffe, tensorflow, tensorflow lite and keras frameworks, and is supported by lattice's AI compiler. This proven set of solutions provides lattice customers with AI applications with fully optimized power consumption and resource efficiency. The software platform is compatible with many of the company's FPGAs (certuspro NX compatibility is planned to be launched later this year).
The application of machine vision at the edge of network requires not only the use of hardware to realize neural network, but also the functions of sensor compatibility, sensor aggregation and image preprocessing. In this regard, lattice provides sufficient flexibility for certuspro NX customers through programmable I / O and SerDes modules. For example, many high-definition image sensors use slvs-ec interface, which is missing from many network edge AI accelerators.
Programmable SerDes also supports various standards for transferring data from the network edge to the system, including coaxpress and 10G Ethernet.
Certuspro NX's on-chip memory size far exceeds that of competitors. Since DRAM operation will increase power consumption and reduce throughput, if all weights are stored on the chip, the neural network can run in the best state and minimize DRAM access. Therefore, customers want to have larger on-chip memory. Lattice's new FPGA can store up to 1 million 8-bit weights - almost twice as many as cyclone V GT or artix-7. Because more weights can be stored inside the chip, certuspro NX can run a larger AI model without accessing DRAM, thus reducing power consumption.
When lattice FPGA really needs to access DRAM, it will use programmable I / O module, which supports lpddr4 and DDR3 memory with speed of 1066 Mbps. Certuspro NX is the first product of its kind to support lpddr4 - a generation ahead of competitors that only provide DDR3 and lower standards. However, on average, this newer technology will increase the power consumption of chips and systems. However, because certuspro NX has larger on-chip memory and optimized memory controller, it can achieve a new energy efficiency by using on-chip and external memory to reduce energy consumption and memory access time. Long term availability is also a concern in many markets, including embedded vision, and lpddr4 relieves this concern.

A key factor in building smart homes and even smart cities is visibility. Most end users prefer unobtrusive IOT sensor designs, and small-size microprocessors are the core of such designs. With an area of only 81 mm2, certuspro NX has the smallest package among similar products supporting SerDes, 33% smaller than cyclone V GT and 84% smaller than artix-7. Small size FPGA further increases the available space of the design, allowing OEM manufacturers to add more functions or reduce the design size.
Industrial Internet of things
The latest generation of industrial Internet of things is characterized by large-scale automation, which benefits from advances in interconnection and data analysis. In order to realize tasks such as automatic sorting and packaging, intelligent factories need thousands of Internet of things devices, which generate and process TB of data every day. The chips driving these devices must be small in size, low in power consumption and high in reliability. In order to prepare customers for Industry 4.0, lattice has adopted the above principles in its latest generation FPGA.
Compared with FPGA competitors based on CMOS technology, certuspro NX adopts fd-soi to reduce power consumption. One way to quantify this power advantage is to look at the power estimators of various suppliers. It is assumed that the design requires 65 K logic units, uses 75% DSP and memory, and runs two 5Gbps SerDes channels. For the design operating at 85 ℃ junction temperature and 125MHz frequency, the total power consumption (dynamic + static) of certuspro NX is 75% less than artix-7 and 65% less than cyclone V GT, as shown in Figure 2.
These data show the powerful power consumption advantages brought by fd-soi process. The manufacturing technology uses an insulating layer in the substrate. Compared with other 28 nm bulk CMOS products, the leakage current can be reduced by up to 75%; Leakage current is the main factor of static power consumption and standby power consumption.
As OEMs improve their product performance by increasing power consumption, Intel and Xilinx FPGAs will exceed their junction temperature threshold faster than lattice FPGAs. With its leading power efficiency, certuspro NX has more power consumption and cooling space, which helps OEMs reduce system size and reduce cooling management costs. In addition, systems operating below junction temperature do not need to install fans prone to mechanical failure.
Heat dissipation is more important for industrial motor control. Motors are often sealed to prevent dust particles from entering and shorten their service life. However, during operation, heat will accumulate in the motor and increase the ambient temperature around the FPGA. Compared with competitive products, lattice's low-power solution allows FPGA to control higher torque motors without overheating.

Figure 2: FPGA power consumption comparison. LC = logical unit. Compared with similar FPGAs of Intel and Xilinx, the power consumption of lattice FPGA is reduced by 65-75%. The power consumption estimation here is calculated when the resource utilization rate is 75% for 5 Gbps dual channel SerDes application at 125MHz and 85 ℃ junction temperature（ Data source: lattice)
Fd-soi also has the additional advantage of eliminating single event upset (SEU) errors. This error occurs when radiation particles pass through the device and interact with the memory or register unit, which will lead to the wrong reversal of the logical state of the device, thus damaging the memory or data path. Compared with artix-7, certuspro NX can reduce the number of soft errors by 99%, without using soft error detection logic and error correction code. This method not only improves the system reliability, but also simplifies the customer design.
The mean time between failures (MTBF) of certuspro NX is 110 times that of artix-7. This feature can meet the reliability requirements of automobile and medical system; Since there is no need for frequent on-site adjustment, it can also reduce the maintenance cost and ensure the normal and continuous operation of key operations. Higher MTBF can also improve the safety of industrial robots, because controlling FPGA to enter an unknown state may lead to machine failure, resulting in personal injury or property loss.
OEM manufacturers usually need to pair FPGA with other system components, which requires high bandwidth of inter chip interface to prevent data flow bottleneck. The new certuspro NX has a four channel PCIe gen3 controller that supports such connections. Its competitors usually only support PCIe Gen2, and the speed of each channel is 50% slower than PCIe gen3. Higher SerDes bandwidth combined with updated PCIe technology allows certuspro NX customers to break the bottleneck of chip interconnection, which may be difficult to achieve with other solutions.
5g application

In order to better serve the wireless network, the base station OEM will separate the control plane from the user plane and allow each plane to expand independently - this is a key feature of 5g network, because these two planes will change every year with the continuous release of new specifications by 3GPP. The control plane is modular, so wireless network providers can split their functions into multiple chips or integrate them into a single chip. It handles a variety of tasks, including authentication, client (UE) session management, and unified data management.
Although the CPU can perform all these functions, it is not as efficient as FPGA. According to industry estimates, OEM manufacturers need efficient hardware because the power consumption of each 5g base station is 70% higher than that of 4G base stations. Considering flexibility and power consumption constraints, base station OEMs usually need FPGA to help enhance processors or ASICs. The power consumption of lattice's new products is lower than that of artix-7 and cyclone V GT, which simplifies the heat dissipation management of the base station.
5g small base station has small space and large data flow. Certuspro NX has the smallest size in similar chip products with SerDes function, is very suitable for small-size design, and the data rate will not be limited. As shown in Figure 3, certuspro NX's leading 75 Gbps SerDes bandwidth is 36% higher than artix-7 and more than twice that of cyclone V GT. For high bandwidth functions such as packet management, lattice FPGA can provide higher throughput and area efficiency by virtue of its larger SerDes bandwidth.

Figure 3: total bandwidth of SerDes. Certuspro NX has more than twice the competitive products and has significant advantages in data intensive operations (such as unified data management in 5g base stations)（ Data source: lattice)
conclusion
Lattice launched certuspro NX mainly to meet the growing market demand of machine vision, industrial Internet of things, 5g cellular network and others. The device's optimized internal memory and lpddr4 can minimize the power consumption of storage intensive operations such as neural networks. Fd-soi technology reduces power consumption and failure rate, making the next generation devices more reliable and lower operation cost. The 10Gbps SerDes of the new FPGA and the industry-leading package size make it very suitable for small systems supporting data processing, such as 5g cellular networks. In addition to excelling in these areas, OEMs can also apply it to many other areas, including defense, automotive and frame grabbing.
The three FPGAs in this paper contain roughly the same number of logic units, but lattice's products have significant advantages because they support lpddr4. In contrast, other devices still use DDR3 memory. Certuspro NX also offers larger internal memory and leading SerDes bandwidth. Customers can not only use lattice FPGA to process and transmit more data, but also reduce power consumption by up to 75% and circuit board area by 84%.
Through the launch of certuspro NX, lattice has injected new vitality into this important field with less investment over the years. Its main competitors have not released any new low-cost architecture products in the past decade, so it has the opportunity to consolidate its market position of the latest product series through new technologies such as PCIe gen3 and lpddr4. This strategy keeps lattice leading in the power consumption and size of low-power FPGA. On the basis of the previous generation of product innovation technology, certuspro NX expands the memory, SerDes and logic functions to better serve emerging markets such as 5g base station, industrial Internet of things and machine vision.